With the guidance from Synopsys professional technical support team, students will build deeper understanding for the development and technology of the Internet of Things.
This event echoes the recent AIoT trend and aims to facilitate students’ hands-on projects combining SoC design and software related to AIOT (AI+IoT, Artificial Intelligence + Internet of Things) applications. To encourage university students to develop innovative designs that meet the needs of semiconductor industry, Synopsys hosts its ARC Design Contest since 2015.ARC Demo Day will be held based on the same contest topic, submission requirement, evaluation criteria, and the same award amount as the original ARC AIoT Design Contest. 30 to demo projects in AIoT applications. Thus, Synopsys invites the contest teams to join ARC Demo Day scheduled on Jul. But as the outbreak slows in Taiwan, students and their advisors hope to continue work on the projects and to complete the learning experiences.
The ARC 710D core is delivered as synthesizable RTL source code (Verilog), and it is fully compatible with industry standard design methodologies and tool flows.The 2020 Synopsys ARC AIoT Design Contest was originally canceled due to the prevention of the Novel Coronavirus disease (COVID-19) outbreak.
The JTAG debug port and optional embedded hardware breakpoints facilitate software debug. The inter-processor communication, multi-processor debug environment, and flexible interfaces enable multi-core designs.
The ARCompact 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bit only instruction sets. The optional ARC XY Advanced DSP subsystem delivers the performance of dedicated DSP cores. Built-in DSP features include instruction and register extensions that accelerate signal processing algorithms. The cacheless design and closely coupled (single-cycle) memories provide fast, predictable computation. The configurable architecture allows SoC designers to include only the processor features that are required for their specific application and user-defined instructions and register extensions can deliver performance improvements for critical routines. Optionally, custom instruction extensions may be incorporated to improve application performance. DSP options enable the 710D core to perform more of the SoC's functions, eliminating separate logic or DSP blocks. Small size, low power and configurable architectural features make the 710D core suitable for multi-core applications. The core is optimized for hard, real-time processing, where high speed and deterministic response are required. The configurable 7-stage ARC 710D processor core is designed for high-performance embedded processing within system-on-chips (SoCs).